1. Field of the Invention
The present invention relates to digital signal buffer amplifiers, and in particular, to digital signal line drivers having an open collector output circuit configuration for sinking an output current and/or wired-OR operation. The present invention further relates to a method of buffering a digital signal and sinking an output current.
2. Description of the Prior Art
Digital signal systems, particularly computers and signal processors, typically communicate their binary instructions and data over some form of shared signal line. Such a shared signal line is often referred to as a "bus," typically consisting of hard-wired connections between the digital signal subsystems which communicate thereby. A bus configuration is preferred so as to minimize interconnections between the various digital signal subsystems.
An example of a signal bus line configured for wired-OR operation is illustrated in FIG. 1. This type of bus line configuration 10 consists of a shared signal line 12 pulled up by a pullup voltage V.sub.PU via pullup resistors R.sub.PU. The digital signal subsystems communicating over the bus line 12 do so by applying their respective output signals A.sub.1 -A.sub.n to circuits S.sub.1 -S.sub.n constituting the functional equivalents of electrical switches. When an output signal A.sub.m (m=1, 2, 3, . . ., n) is active (e.g., a logical "one"), its associated switch S.sub.m closes, thereby shorting the bus line 12 to circuit ground. This pulls the bus line 12, and therefore the bus line output signal B (e.g., output voltage V.sub.0), down to a logical "zero."
The bus line configuration 10 of FIG. 1 is a wired-OR configuration. Whenever any of the individual digital subsystem output signals A.sub.m become active (i.e., A.sub.1 or A.sub.2 or A.sub.3 or . . . or A.sub.n), the associated switch S.sub.m pulls the bus line 12 down to a logical zero. Such a configuration 10 is sometimes referred to as "backplane logic" since the backplane wiring interconnecting the switches S.sub.1 -S.sub.n and thereby constituting the bus line 12 is actually part of the logic constituting the wired-OR configuration 10.
In a wired-OR logic configuration 10 such as that illustrated in FIG. 1, the circuit constituting a switch S.sub.m typically has an open collector output circuit configuration. The collector of the output transistor is coupled directly to the bus line 12 and the emitter is coupled to circuit ground. When the circuit's driving signal A.sub.m is active, the output transistor is turned on in its saturated mode and its collector-to-emitter voltage ("Vcr") becomes virtually zero, thereby causing its collector to pull the bus line 12 down to a logical zero.
In the bus line configuration 10 of FIG. 1, the pullup voltage V.sub.PU is typically two volts and two pullup resistors R.sub.PU are used, each being in the range of 30-40 ohms and physically located near opposing ends of the backplane wiring constituting the bus line 12. A typical configuration 10 includes 32 switches S.sub.m (i.e., m=32) and each switch S.sub.m must be capable of sinking up to 100 milliamperes of current from the bus line 12 at a low output voltage V.sub.0. Therefore, under dynamic circuit 10 operating conditions, regardless of whether only one or all 32 switches S.sub.m are active, the pullup resistors R.sub.PU with values in the range of 30-40 ohms will substantially match the bus line 12 to the net circuit impedance presented by the switches S.sub.m.
An example of a transistor-transistor logic ("TTL") circuit constituting a switch S.sub.m is illustrated in FIG. 2. This bus line driver circuit 20 consists of: an input resistor 22; an input bipolar junction transistor ("BJT") 24; a biasing resistor 26; an output BJT 28; an output isolation diode 30; an output pullup resistor 32; and an output pullup diode 34. The input signal A.sub.m is a voltage having nominal TTL values. The output signal B.sub.m has an output voltage V.sub.o having a logical zero value of approximately 800 millivolts which is primarily dependent upon the conduction characteristics of the output isolation diode 30 and output BJT 28, and a logical one value of approximately two volts which is primarily dependent upon the pullup voltage V.sub.PU of the bus line 12. The biasing resistor 26 and output pullup resistor 32 are pulled up to a supply voltage V+, which is typically five volts for TTL types of signals.
When the input signal A.sub.m is inactive, i.e., at a logical zero (e.g., a TTL "low" of approximately zero volts dc), no input current flows through the input resistor 22 into the base of the input BJT 24. Thus, the input BJT 24 is turned off and no emitter current flows therefrom, and therefore, no base current flows into the output BJT 28. With no base current, the output BJT 28 is also turned off.
With the output BJT 28 turned off, the output voltage V.sub.o is at a logical one, the voltage value for which is determined by the pullup voltage V.sub.PU for the bus line 12. This is because the output pullup voltage V+ is higher than the pullup voltage V.sub.PU for the bus line 12, which causes the output pullup diode 34 to be forward-biased but the output isolation diode 30 to be reverse-biased. The reverse-biased output isolation diode 30 causes the bus line 12 to see a virtual open circuit at the anode of the output isolation diode 30.
When the input signal A.sub.m is active, i.e., at a logical one (e.g., a TTL "high" of approximately two volts dc), an input current flows through the input resistor 22 into the base of the input BJT 24. This turns the input BJT 24 on, resulting in emitter current flowing therefrom, and therefore, base current flowing into the output BJT 28. With sufficient base current, the output BJT 28 turns on in a saturated mode, thereby causing its voltage at its collector V.sub.CE to represent a logical zero. Based upon the known and/or designed electrical operating characteristics of the BJTs 24, 28 and the level of the input signal A.sub.m, appropriate values for the input 22 and biasing 26 resistors can be selected so as to cause the output BJT 28 to turn on in its saturated mode.
With the output BJT 28 turned on in its saturated mode, its output voltage V.sub.CE is at a logical zero and current flows into its collector. This collector current is the sum of the currents flowing through the output pullup diode 34 and output isolation diode 30, which are now forward-biased by their respective pullup voltages V+, V.sub.PU. Thus, with the output isolation diode 30 and output BJT 28 both turned on, the output voltage V.sub.0 becomes a logical zero, the value for which is determined by the "on" voltage V.sub.D of the output isolation diode 30 and the saturated output voltage V.sub.CE of the output BJT 28. The output isolation diode 30 typically consists of a Schottky diode. Therefore, the output voltage V.sub.0 is typically less than one volt.
The output isolation diode 30 is connected as shown in order to reduce the capacitive loading of the bus line 12 otherwise caused by the collector of the output BJT 28. As described above, when the circuit 20 is in its "off" state the output pullup voltage V+ causes the output isolation diode 30 to be reverse-biased. When the diode is reverse-biased its depletion region at its p-n junction becomes wider, and therefore, its p-n junction's capacitance is reduced. With this reduced capacitance, the capacitive load on the bus line 12, as presented thereto by the "off" output isolation diode 30, is reduced. Thus, the signal line driver circuit 20 of FIG. 2 presents minimal capacitive loading to the bus line 12.
Using a signal line driver circuit 20 as shown in FIG. 2 presents three problems. First, to effectively sink current from the bus line 12 at a low output voltage V.sub.0, the output BJT 28 must operate in a fully saturated mode. This requires that a significant base current be supplied to the output BJT 28, which in turn, requires a significant emitter current from the input BJT 24. Therefore, the power supply providing the biasing voltage V+ must provide a significant current to the collector of the input BJT 24. This significant collector current is multiplied many times in practice since a typical digital system uses many circuits 20 of the type illustrated in FIG. 2. Thus, this power supply must have the capability of supplying a large current.
Having the capacity to produce a large supply current makes a power supply much more expensive. Moreover, as the current capacity increases, the waste heat generated as a result can increase exponentially. This results in greater cooling requirements which in turn often results in greater unit weight due to heavier heatsinks and larger blowers. Hence, the greater the current capacity is, the more expensive, hotter and heavier the power supply must be.
Second, as is well known in the art, the conductivity of a BJT varies proportionately with temperature. Therefore, at low temperatures the conductivity of a BJT is substantially reduced. This causes the BJT's forward-bias, base-emitter junction voltage ("V.sub.BE ") to increase. This in turn causes the forward biasing of the base-emitter junction, for a given base current, to decrease, thereby producing a decrease in the collector and emitter currents. This further in turn causes the collector-emitter voltage ("V.sub.CE ") of the BJT to increase.
Therefore, at low temperatures, the output voltage V.sub.0 of the circuit 20 increases since the output voltage V.sub.CE of the output BJT 28 increases, as described above. This is undesirable since often the specified voltage range of the circuit output voltage V.sub.0 is quite narrow, and frequently has a maximum value which may easily be exceeded when the transistor's output voltage V.sub.CE increases at low temperatures.
Third, due to the temperature dependent conductivities of the BJTs 24, 28 and the corresponding variations in the V.sub.BE for each, the input-to-output signal propagation delay also varies with temperature. In other words, as the operating temperature varies, the time difference between when input signal A.sub.m becomes active and when the output BJT 28 turns on (i.e., the input-to-output signal propagation delay) also varies. Typically, over the operating temperature range of -55.degree. C. to +125.degree. C. the input-to-output signal propagation delay variation will be in the range of 4-5 nanoseconds. This amount of variation may be undesirable, particularly if the circuit 20 must operate at high frequency.